Design and Implementation of a Digital Phase Locked Loop for GPS Synchronization

Authors

  • Mouloud CHALLAL Institute of Electrical and Electronic Engineering, University M'Hamed BOUGARA Boumerdes
  • Abderrahmane OUADI
  • Hamid BENTARZI
  • Abderazak CHERFI
  • Omar SAIDI

DOI:

https://doi.org/10.51485/ajss.v10i1.233

Keywords:

Digital Phase-Locked Loop, Phase Frequency Detector, RC Low-Pass Filter, Relaxation Voltage Controlled Oscillator

Abstract

In this paper, a Digital Phase-Locked Loop (DPLL) for GPS synchronization is designed, implemented and tested. It consists of a Phase Frequency Detector (PFD), an RC Low-Pass Filter (LPF), and a Relaxation Voltage Controlled Oscillator (VCO). The analysis, design, and examination of each block are carried out, resulting in a successful assembly of the entire DPLL circuit. The designed PLL is simulated, measured, and then compared with the experimental observations using LM565 IC. The findings demonstrate the PLL capability to achieve frequency synchronization with minimal phase error at the desired frequency of 1 KHz, along with a wide lock-in range.

Downloads

Download data is not yet available.

Author Biography

Mouloud CHALLAL, Institute of Electrical and Electronic Engineering, University M'Hamed BOUGARA Boumerdes

Mouloud CHALLAL, IEEE Senior Member, received the Telecommunications Engineering degree in April 1999 from University of Science and Technology Houari Boumediene (Bab-Ezzouar, Algeria), the M.S degree (Magister) in December 2001 from National Polytechnic School of Algiers (Algeria), and the doctorate degree in March 2012 from University M'Hamed BOUGARA Boumerdes (Boumerdes, Algeria).
       He joined the Department of Electrical & Electronic Engineering (DGEE), UMBB, as Lecturer during 2004-2007, Assistant Professor during 2008-2012, Associate professor during 2012-2018 at the Institute of Electrical and Electronic Engineering (IGEE, formerly called the National Institute of Electricity and Electronics - INELEC), UMBB and then as full professor in Telecommunication since 2019. Moreover, he took many responsibilities position such as From Sep. 2007 to Mar. 2008, Vice-head of DGEE, responsible of master degree program in Telecommunications at IGEE during 2016 to 2017, Vice-Director in charge of studies and students' related issues at IGEE during 2017 to 2018 and then as Director of the IGEE since Sep. 2018.
       Dr. Challal has authored/co-authored over 85 research papers in international conferences and journals. His current research interests include antennas and RF/Microwaves circuits’ analysis, design, and measurement. He is a founding member of the creation of the “IEEE Algeria Sub-section” where he held the post, volunteer, treasurer from 2012 to 2014. He is also among active elements in the formation of both the “IEEE Algeria Section”, approved by IEEE in November 2015 and the “Association Algérienne de Génie Électrique et Électronique (AAGEE)”, approved by Interior ministry in November 2015. In addition, he is a counselor of IEEE Student Branch of University of Boumerdes since October 2014 (date of approval). He is a member of European Microwave Association (EuMA) since 2008 and reviewer for several refereed international journals and conferences.

Downloads

Published

2025-03-31

How to Cite

[1]
CHALLAL, M., OUADI, A. , BENTARZI, H., CHERFI , A. and SAIDI, O. 2025. Design and Implementation of a Digital Phase Locked Loop for GPS Synchronization. Algerian Journal of Signals and Systems . 10, 1 (Mar. 2025), 18-23. DOI:https://doi.org/10.51485/ajss.v10i1.233.

Issue

Vol. 10 No. 1 (2025)

Section

Articles

License

Copyright (c) 2025 Mouloud CHALLAL, Abderrahmane OUADI, Hamid BENTARZI, Abderazak CHERFI , Omar SAIDI

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.